1. Field of the Invention
The present invention relates to stack structures of circuit boards, and more particularly, to a stack structure of circuit boards each embedded with a semiconductor component.
2. Description of the Prior Art
Electronic products nowadays have a trend toward minimization. With the sizes of electronic products decreasing, there is a need to embed, more densely than before, semiconductor components with various functions in a circuit board. To meet the need, manufacturers mount at least two semiconductor chips on a chip carrier (a substrate or leadframe, for example) of a single package, upwardly stack the semiconductor chips one by one on the chip carrier, and then perform wire bonding to achieve electrical connection.
Referring to FIG. 1, it shows a cross-sectional view illustrating a multi-chip semiconductor package 1 disclosed in U.S. Pat. No. 5,323,060. The semiconductor package 1 comprises a first semiconductor chip 12a mounted on a circuit board 11. The first semiconductor chip 12a is electrically connected to the circuit board 11 by a plurality of first bonding wires 13a. Disposed on the first semiconductor chip 12a in a stacking manner is a second semiconductor chip 12b, with an adhesive layer 14 applied therebetween. The adhesive layer 14 is typically one of an epoxy resin adhesive and an adhesive tape. Afterward, the second semiconductor chip 12b is electrically connected to the circuit board 11 by a plurality of second bonding wires 13b. However, the wire bonding process for the first semiconductor chip 12a has to be performed before the second semiconductor chip 12b. In other words, both die bonding and wire bonding have to be carried out to the chips one by one and level by level, thus making the process complex. In addition, considering that the first semiconductor chip 12a, the adhesive layer 14, and the second semiconductor chip 12b are in turn carried on the circuit board 11, and that it is necessary to prevent the second semiconductor chip 12b from coming into contact with the first bonding wires 13a, the adhesive layer 14 has to have a thickness sufficient to allow the second semiconductor chip 12b to be higher than the loop height of the first bonding wires 13a. In consequence, the overall thickness of the semiconductor package 1 turns out to be against the trend of miniaturization of semiconductor devices. Also, owing to poor control of the thickness of the adhesive layer 14, a short circuit may arise if the second semiconductor chip 12b comes into contact with the first bonding wires 13a, or when the first bonding wire 13a comes into contact with the second bonding wires 13b. 
Owing to circuit integration, it is becoming more common to embed a semiconductor component in a carrier board. Referring to FIG. 2, which is a schematic view showing a conventional circuit board structure with a semiconductor component embedded therein. As shown in drawing, at least one cavity 200 is formed in a carrier board 20 and configured to receive a semiconductor component 21. The semiconductor component 21 has an active surface 21a formed with a plurality of electrode pads 212. A dielectric layer 22 is applied over the carrier board 20 and the active surface 21a. Formed on the dielectric layer 22 is a circuit layer 23 having a plurality of conductive structures 231 for electrical connection with the electrode pads 212. In doing so, a plurality of circuit layers are built up so as to form a multilayer circuit board.
Nevertheless, as regards the aforesaid process, since a single carrier board 20 embedded with a semiconductor component 21 has very limited electronic functions, it is necessary to use more than one semiconductor component 21 in order to enhance the electrical functions of the carrier board 20, which in turn entails forming a plurality of cavities 200 in the carrier board 20. However, a problem arises that the area of the carrier board 20 is very limited and not to be increased, thus limiting the increase and development of the electrical functions of the carrier board 20.
Accordingly, an issue which needs an efficient solution is related to an attempt to embed a semiconductor component in a circuit board and enhance the electrical functions thereof.